Packaging technologies for a semiconductor integrated device have been continuously developed to satisfy the demands for mounting efficiency and miniaturization. Various semiconductor interconnect technologies have been developed as the miniaturization and high performance resulting from recent development trends in the semiconductor chip devices technology.
Interconnects and packaging-related issues are among factors that determine not only the number of circuits that can be integrated in a semiconductor die or “chip,” but also the chip performance. These issues have gained importance as advances in chip design have led to reduced sizes of transistors and enhanced chip performance. Practitioners in the art have come to realize that merely having a fast chip does not necessarily result in a fast system; a fast chip must also be supported by equally fast and reliable electrical connections. Essentially, on-chip connections in conjunction with those of the chip's associated packaging supply the chip with signals and power, provide signals from the chip and redistribute the tightly spaced or pitched terminals or bond pads of the chip to the terminals of a carrier substrate such as a printed circuit board.
Though much effort has been expended by practitioners working on making through-silicon vias (TSV) for various technology offerings, there are few that are presently in manufacturing. These are mainly used for interposers, i.e., an interface between a chip and a package that allows an amount of expansion difference between the package and the die or chip, and which accommodates the thermal coefficient of expansion difference between the silicon chip and the package.
The main thrust of current work resides in developing TSVs that are fabricated in a way where they can be incorporated in the functional chips, allowing the chips to be stacked or joined in order to increase the functionality of the chip set. This includes reduced power and in kind the reduction of heat, while offing an increase in performance of the entire set.
When stacking chips, the TSV connections are not necessarily vertically aligned. To simply state it, if there are three TSVs in a chip stack of a multiple of chips, the first TSV may need to be electrically connected to the package, the second may require connecting a first chip, a second chip and a third which may need to be connected to the first and third chips. A problem arises if a TSV is required to connect the chip interconnects within the die or chip. Other TSVs may also be independently added to the same chip to be etched through the chip. This can be achieved with multiple steps, however with the addition of these steps there is associated yield loss and expense. Furthermore, if there is the requirement of a passive element that needs to be fabricated after the TSV, it can become problematic because of the topography, if the conductivity requirements specify a copper TSV. The large copper feature lends itself to topography creation due to chemical mechanical polish (CMP). Therefore, two issues include stopping the large via etch that needs to be electrically connected to the BEOL interconnections while also having large TSV's that will be etched through the entire chip build, and processing a passive element post TSV processing, such as a MIM capacitor.
In summary, TSV technology is important in creating 3D packages and 3D integrated circuits in a smaller footprint to maintain a superior electrical performance. Chip-to-chip connections that have traditionally been accomplished with wire bonding often to multiple stacked die are limited in terms of the number of connections and electrical performance. Other existing structures and processes are characterized by vias etched through the silicon (and often many layers of metal and dielectric) using a deep-RIE (BOSCH) process, with an insulating layer deposited followed by a metal liner and, then, continuing with copper damascene processing.
Therefore, there is a need for a structure and a method for providing substrate interconnect using an integrated conductive hardmask stack for patterning TSVs to provide electrical connections between an integrated circuit chip and a package.